View AS15261_4978453.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AS1526, AS1527
1 0 - B i t , S i n g l e S u p p l y, L o w - P o w e r, 7 3 k s ps A/ D Conv e rters
D a ta S he e t
1 General Description
The AS1526/AS1527 are low-power, 10-bit, 73ksps analog-to-digital (A/D) converters specifically designed for single-supply A/D applications. Superior AC characteristics, very low power consumption, and robust packaging make these ultra-small devices perfect for battery-powered analog-data collection devices. The integrated successive-approximation register (SAR) and a fast (1.5s) sampling track/hold time provide an economic and highly-reliable A/D conversion solution. The AS1526/AS1527 operate from a single 2.7 to 3.6V supply. The AS1527 requires an external reference, using less power than the AS1526, however, the AS1526 features an internal 2.5V reference. As with the AS1527, the AS1526 can also be used with an external reference, which uses the input range 0V to VREF, including the positive supply range. The AS1527 consumes only 3mW (VDD = 3V) at the 73ksps maximum sampling speed. Both devices feature a low-current (0.3A) shutdown mode, which reduces power consumption at slower throughput rates. Data accesses are made via the standard, high-speed 3-wire serial interface, which is SPI-, QSPI-, and Microwire-compatible. Both devices contain an internal clock, however, both devices also support an external clock for increased flexibility. The AS1526/AS1527 are available in an 8-pin SOIC-150 package.
2 Key Features
! ! ! ! ! !
10-Bit Resolution with 7.5s Conversion Time Sampling Rate: 73ksps Straight Binary (Unipolar) Data Format Single-Supply Operation:+2.7 to +3.6V Internal 2.5V Reference (AS1526) Low Power-Consumption: - 4mW (73ksps, AS1526) - 3mW (73ksps, AS1527) - 66W (1ksps, AS1527) - 1W (Shutdown Mode) Integrated Track/Hold Amplifier Internal Clock SPI/QSPI/Microwire 3-Wire Serial Interface Operating Temperature Range: -40 to +85C 8-pin SOIC-150 Package
! ! ! ! !
3 Applications
The devices are ideal for remote sensors, data-acquisition, data logging devices, lab instruments, or for any other space-limited A/D devices with low power consumption and single-supply requirements.
Figure 1. Block Diagram and Pin Assignments
1 VDD 7 CSN 8 SCLK 3 SHDNN Control Logic Internal Clock SHDNN 3 2 AIN 4 REF Track/ Hold 10-Bit SAR 2.5V Ref 5 GND AS1526 only Output Shift Register 6 DOUT AIN 2 7 CSN
AS1526/AS1527
VDD 1 8 SCLK
AS1526/ AS1527
6 DOUT
REF 4
5 GND
www.austriamicrosystems.com
Revision 1.03
1 - 21
AS1526/AS1527 Data Sheet
Contents
1 General Description 2 Key Features 3 Applications ..............................................................................................................................1 .........................................................................................................................................1 ...........................................................................................................................................1 ...........................................................................................................................3
...................................................................................................................................................3 ....................................................................................................................................................3
4 Pinout and Packaging
Pin Assignments Pin Descriptions
5 Absolute Maximum Ratings 6 Electrical Characteristics
Timing Characteristics
..................................................................................................................4
.......................................................................................................................5 .........................................................................................................8
..........................................................................................................................................7
7 Typical Operating Characteristics 8 Detailed Description
Analog Input Track/Hold
............................................................................................................................ 11
........................................................................................................................................................11 ...........................................................................................................................................................12 .....................................................................................................................................................12 ..............................................................................................................................................12 ................................................................................................................................................14 ....................................................................................................................................14 ......................................................................................................................15
Input Protection ..............................................................................................................................................12 External Clock
Timing and Control Transfer Function
Reducing Supply Current External Reference Initialization
Internal 2.5V Reference (AS1526)
.............................................................................................................................................15
9 Application Information
Serial Interface
.......................................................................................................................16
.........................................................................................................................................................16 ....................................................................................................................................................16
Serial Interface Configuration .........................................................................................................................16 SPI and Microwire Interfaces .........................................................................................................................16 QSPI 17 Layout Considerations ........................................................................................................................................18 .......................................................................................................................19 Package Drawings and Markings
10 Ordering Information
........................................................................................................................20
www.austriamicrosystems.com
Revision 1.03
2 - 21
AS1526/AS1527 Data Sheet - P i n o u t
and Packaging
4 Pinout and Packaging
Pin Assignments
Figure 2. Pin Assignments (Top View)
VDD 1
8 SCLK
AIN 2
7 CSN
AS1526/ AS1527
SHDNN 3 6 DOUT
REF 4
5 GND
Pin Descriptions
Table 1. Pin Descriptions Pin Number 1 2 Pin Name VDD AIN Description Positive Supply Voltage. +2.7 to +3.6V Sampling Analog Input. 0V to VREF range. Three-Level Shutdown Input. Pulling this pin low puts the AS1526/AS1527 in shutdown mode, down to 4A (max) supply current. The devices are fully operational with this pin high or floating. Note: For the AS1526, pulling this pin high enables the internal reference; letting this pin float disables the internal reference allowing for the use of an external reference. See also pin 4. A/D Conversion Reference Voltage. This pin serves as the internal 2.5V reference output for the AS1526; bypass this pin with a 4.7F capacitor. This pin also serves as the external reference voltage input for the AS1527, or for AS1526 if the internal reference is disabled. Bypass this pin with a minimum of 0.1F when using an external reference. See also pin 3. Analog and Digital Ground Serial Data Output. Data changes state at SCLK's falling edge. Note: This pin is high-impedance when pin CSN is high. Active-Low Chip Select. The falling edge of this pin initiates a conversion. Note: When this pin is high, DOUT is high-impedance. Serial Clock Input. This pin clocks data out at rates up to 2.1MHz.
3
SHDNN
4
REF
5 6 7 8
GND DOUT CSN SCLK
www.austriamicrosystems.com
Revision 1.03
3 - 21
AS1526/AS1527 Data Sheet - A b s o l u t e
Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VDD to GND AIN to GND REF to GND Digital Inputs to GND DOUT to GND DOUT Current Continuous Power Dissipation (TAMB = +70C) Operating Temperature Range Storage Temperature Range -40 -60 Min 0.3 -0.3 -0.3 -0.3 -0.3 -25 Max +5 VDD + 0.3V VDD + 0.3V VDD + 0.3V VDD + 0.3V +25 471 +85 +150 Units V V V V V mA mW C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices". Derate 5.88mW/C above +70C Comments
Package-Body Peak Temperature
260
C
www.austriamicrosystems.com
Revision 1.03
4 - 21
AS1526/AS1527 Data Sheet - E l e c t r i c a l
Characteristics
6 Electrical Characteristics
VDD = +2.7 to +3.6V, 73ksps, fSCLK = 2.1MHz (50% duty cycle); AS1526:4.7F capacitor at REF, AS1527: external reference; VREF = 2.5V applied to REF; TAMB = TMIN to TMAX (unless otherwise specified). Table 3. Electrical Characteristics Symbol DC Accuracy
1
Parameter
Conditions
Min
Typ
Max
Units
Resolution Relative Accuracy DNL
2
10 0.5 No missing codes over temperature 1 2 2 1
Bits LSB LSB LSB LSB ppm/C
Differential Non-Linearity Offset Error Gain Error
3
Gain Temperature Coefficient Dynamic Specifications (10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps, fSCLK =2.1MHz) SINAD THD SFDR Signal-to-Noise + Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth Conversion Rate tCONV tACQ Conversion Time Track/Hold Acquisition Time Throughput Rate tAP Aperture Delay Aperture Jitter Analog Input Input Voltage Range Input Capacitance Internal Reference (AS1526 only) REF Output Voltage REF Short-Circuit Current REF Temperature Coefficient Load Regulation CREFBYP
6 4
61 Up to the 5th harmonic -70 70 -3dB rolloff 2.5 2.5
dB dB dB MHz MHz
5.5
7.5 1.5
s s ksps ns ps
fSCLK = 2.1MHz Figure 27 on page 13 7 <50
73
0 21
VREF
V pF
TAMB = +25C
5
2.47
2.50
2.53 45
V mA ppm/C mV F
AS1526 0 to 0.2mA output load 4.7
30 0.35
Capacitive Bypass at REF
External Reference (VREF = 2.5V) Input Voltage Range Input Current Input Resistance REF Input Current in Shutdown CREFBYP Capacitive Bypass at REF SHDNN = 0V 0.1 18 1.00 100 25 0.01 10 VDD + 50mV 150 V A k A F
www.austriamicrosystems.com
Revision 1.03
5 - 21
AS1526/AS1527 Data Sheet - E l e c t r i c a l
Characteristics
Table 3. Electrical Characteristics (Continued) Symbol Parameter Conditions Min Typ Max Units
Digital Inputs: SCLK, SHDNN, CSN VIH VIL VHYST IIN CIN VSH VSL SCLK, CSN Input High Voltage SCLK, CSN Input Low Voltage SCLK, CSN Input Hysteresis SCLK, CSN Input Leakage SCLK, CSN Input Capacitance SHDNN Input High Voltage SHDNN Input Low Voltage SHDNN Input Current VSM VFLT SHDNN Input Mid Voltage SHDNN Voltage, Floating SHDNN Max Allowed Leakage, Mid Input Digital Output: DOUT VOL VOH IL COUT Output Voltage Low Output Voltage High Tri-State Leakage Current Tri-State Output Capacitance ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CSN = VDD CSN = VDD
7 7
0.7x VDD 0.3x VDD 0.2 VIN = 0V or VDD 0.01 1 15 VDD 0.4 0.4 SHDNN = 0V or VDD 1.1 SHDNN = float SHDNN = float VDD/2 50 4.0 VDD 1.1
V V V A pF V V A V V nA
0.4 0.8 VDD 0.5 0.01 10 15
V V A pF
Power Requirements VDD Supply Voltage Int. Reference (AS1526), VDD = 3.6V IDD Supply Current External Reference, VDD = 3.6V Shutdown mode, VDD = 3.6V PSR Power-Supply Rejection
8
2.7 1.4 1.0 0.3 1
3.6 2.0 1.4 2
V mA A mV
VDD = VDDMIN to VDDMAX, full-scale input
1. Tested at VDD = +2.7V. 2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. 3. Offset nulled. 4. Achievable with standard timing (see Figure 25 on page 13). 5. Sample tested at 0.1% AQL. 6. External load should not change during conversion for specified accuracy. 7. Guaranteed by design; not subject to production testing. 8. Measured as [VFS(VDDMIN) - VFS(VDDMAX)] with external reference.
www.austriamicrosystems.com
Revision 1.03
6 - 21
AS1526/AS1527 Data Sheet - E l e c t r i c a l
Characteristics
Timing Characteristics
VDD = +2.7 to +3.6V, TAMB = TMIN to TMAX (unless otherwise specified). Table 4. Timing Characteristics Parameter Acquisition Time
1
Symbol tACQ tDO tDV tTR fSCLK tCH tCL tCS0 tSTR tCS
Conditions
Min 1.5
Typ
Max
Units s
SCLK Falling-to-DOUT Valid CSN Falling-to-Output Enable CSN Rising-to-Output Disable SCLK Clock Frequency SCLK Pulse Width High SCLK Pulse Width Low SCLK Low-to-CSN Falling Setup Time DOUT Rising-to-SCLK Rising CSN Pulse Width
2
Figure 3, CLOAD = 50pF Figure 3, CLOAD = 50pF Figure 4, CLOAD = 50pF
20
200 240 240
ns ns ns MHz ns ns ns ns ns
0 200 200 50 0 240
2.1
1. To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired 2. Guaranteed by design; not subject to production testing. Figure 3. DOUT Enable-Time Load Circuits
+2.7V DOUT 6k CLOAD 50pF DOUT DGND GND CLOAD 50pF 6k
High-impedance to VOH and VOL to VOH DGND High-impedance to VOL and VOH to VOL
Figure 4. DOUT Disable-Time Load Circuits
DOUT 6k CLOAD 50pF DOUT DGND VOH to high-impedance DGND VOL to high-impedance GND CLOAD 50pF +2.7V
6k
www.austriamicrosystems.com
Revision 1.03
7 - 21
AS1526/AS1527 Data Sheet - Ty p i c a l
Operating Characteristics
7 Typical Operating Characteristics
VDD = 3.0V, VREF = 2.5V, fSCLK = 2.1MHz, CLOAD = 50pF, TAMB = +25C (unless otherwise specified). Figure 5. Integral Nonlinearity vs. Digital Output Code Figure 6. Differential Nonlinearity vs. Digital Output Code
1 0.8 0.6 1 0.8 0.6
0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 256 512 768 1024
DNL (LSB) .
0.4
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 256 512 768 1024
INL (LSB) .
Digital Output Code
Figure 7. FFT @ 1kHz
0 -20 -40
Fsample = 80.8ksps NFFT = 16384
Digital Output Code
Figure 8. FFT @ 10kHz
0 -20 -40
Fsample = 80.8ksps NFFT = 16384
FFT (dBC) .
-60 -80 -100 -120 -140 -160 0 10 20 30 40
FFT (dBC) .
-60 -80 -100 -120 -140 -160 0 10 20 30 40
Input Signal Frequency (kHz)
Figure 9. ENOB vs. VREF
9.95 9.92
Input Signal Frequency (kHz)
Figure 10. ENOB vs. Input Signal Frequency
9.95 9.94
ENOB (Bit) .
9.86 9.83 9.8 9.77 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
ENOB (Bit) .
9.89
9.93 9.92 9.91 9.9 9.89 0 10 20 30 40
Reference Voltage (V)
Frequency (kHz)
www.austriamicrosystems.com
Revision 1.03
8 - 21
AS1526/AS1527 Data Sheet - Ty p i c a l
Operating Characteristics
Figure 11. Supply Current vs. Supply Voltage
2
Figure 12. Supply Current vs. Temperature
2
.
Supply Current (mA)
1.5
Supply Current (mA) .
Internal Reference
1.5
Internal Reference
1
External Reference
1
External Reference
0.5
0.5
0 2.7 3 3.3 3.6
0 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
Figure 14. Shutdown Supply Current vs. Temperature
2
Figure 13. Shutdown Supply Current vs. Supply Voltage
1
Shutdown Supply Current (A)
.
0.75
Supply Current (A) .
2.7 3 3.3 3.6
1.5
0.5
1
0.25
0.5
0
0 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
Figure 16. Offset Voltage vs. Temperature
0.5
Figure 15. Offset Error vs. Supply Voltage
0.3 0.2 0.1 0 -0.1 -0.2 2.7 3 3.3 3.6
0.4
.
Offset Error (LSB)
Offset Error (LSB) .
0.3
0.2
0.1
0 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
www.austriamicrosystems.com
Revision 1.03
9 - 21
AS1526/AS1527 Data Sheet - Ty p i c a l
Operating Characteristics
Figure 17. Gain Error vs. Supply Voltage
0.2
Figure 18. Gain Error vs. Temperature
0.2
Gain Error (LSB) .
0
Gain Error (LSB) .
2.7 3 3.3 3.6
0.1
0.1
0
-0.1
-0.1
-0.2
-0.2 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
Figure 19. Internal Reference Voltage vs. Supply Voltage Figure 20. Internal Reference Voltage vs. Temperature
2.51
.
2.52
Internal Reference Voltage (V)
2.505
Internal Reference Voltage (V).
2.7 3 3.3 3.6
2.51
2.5
2.5
2.495
2.49
2.49
2.48 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
Figure 22. Integral Nonlinearity vs. Temperature
0.5
Figure 21. Integral Nonlinearity vs. Supply Voltage
0.5 0.4
0.4
INL (LSB) .
0.3 0.2 0.1 0 2.7 3 3.3 3.6
INL (LSB) .
0.3
0.2
0.1
0 -40 -15 10 35 60 85
Supply Voltage (V)
Temperature (C)
www.austriamicrosystems.com
Revision 1.03
10 - 21
AS1526/AS1527 Data Sheet - D e t a i l e d
Description
8 Detailed Description
The AS1526/AS1527 analog-to-digital converters have two modes of operation:
!
Normal A/D Conversion Mode - Pulling pin SHDNN high or leaving it open puts the device into normal A/D conversion mode. Shutdown Mode - Pulling pin SHDNN low shuts the device down and reduces supply current below 2A (VDD 3.6V).
!
Note: Pulling pin CSN low starts a conversion. The conversion result is available at pin DOUT in unipolar serial format (see Timing and Control on page 12).
Figure 23 shows a basic configuration for the AS1526/AS1527. The integrated input track/hold circuitry and a successive-approximation register (SAR) circuitry convert analog input signals to a digital 10-bit output. No external-hold capacitor is needed for the track/hold circuit. The devices convert analog input signals in the 0V to VREF range in 13s (includes track/hold acquisition time). The AS1526 internal reference is trimmed to 2.5V; the AS1527 requires an external reference. Both devices can accept external reference voltages from 1.0V to VDD. The serial interface requires only three digital lines (at pins SCLK, CSN, and DOUT) and provides a simple microprocessor interface.
Figure 23. Operational Diagram
1 + 4.7F 0.1F 2 AIN 3 SHDNN Reference Input Required for AS1527, Optional for AS1526 7 CSN VDD 8 SCLK
+2.7 to +3.6V
AS1526/ AS1527
6 DOUT
4 REF AS1526 - 4.7F AS1527 - 0.1F
5 GND
Analog Input
Figure 24 illustrates the integrated comparator sampling architecture. The full scale input voltage is set by the voltage at pin REF.
Figure 24. Equivalent Input Circuit
REF
CHOLD 13pF AIN CSWITCH 14pF -+ Sample Switch CHOLD 13pF GND -+ S&H and DAC CSWITCH includes all parasitics RIN
+ - Comparator
www.austriamicrosystems.com
Revision 1.03
11 - 21
AS1526/AS1527 Data Sheet - D e t a i l e d
Description
The devices' input tracking circuitry has a 2.5MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed transient events) and measure periodic signals with bandwidths exceeding the devices' sampling rate.
Note: Anti-aliasing filtering should be used to avoid aliasing of unwanted high-frequency signals into the bandwidth of interest.
Input Protection
Internal protection diodes clamp the analog input to VDD and GND, allowing the input to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the input must not exceed VDD by more than 50mV, or be lower than GND by 50mV.
Note: If the analog input exceeds the supply by 50mV, limit the input current to 2mA.
Track/Hold
In track mode, the analog signal is acquired and stored in the internal hold capacitors. During acquisition, the analog input at pin AIN charges capacitor CHOLD (see Figure 24 on page 11). Bringing CSN low ends the acquisition interval and the charge on CHOLD represent the sampled input voltage. In hold mode, the T/H switches are opened thus the input is disconnected from the capacitor CHOLD. During this mode the successive approximation is performed which in turn forms a digital representation of the analog input signal. At the end of the conversion, the input side of the in meantime discharged CHOLD switches back to AIN, and CHOLD charges to the input signal again. The maximum time for the T/H to acquire a signal (tACQ) is a function of how quickly its input capacitance is charged. tACQ increases proportionally to the input signal's impedance, and at higher impedances more time must be allowed between conversions. tACQ is also the minimum time needed for the signal to be acquired, and is calculated by:
tACQ = 7(RS + RIN) x 21pF (EQ 1) Where: RIN = 4.5k RS = the input signal's source impedance. tACQ is never less than 1.5s. Source impedances < 1k do not significantly affect the AC performance of the devices. Note: Higher source impedances can be used if a 0.01F capacitor is connected to the analog input. Note that the input capacitor forms an RC filter with the input source impedance, limiting the devices' input signal bandwidth.
External Clock
The AS1526/AS1527 do not require an external clock for analog-to-digital data conversion. This allows the microprocessor to read back the conversion results at any clock rate from up to 2.1MHz at any time. The clock duty cycle is unrestricted if each clock phase is at least 200ns.
Note: The external clock must not be run while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled by digital inputs CSN and SCLK. Refer to Figures 25 - 27 (see page 13) for graphical timing and control information. The falling edge on pin CSN initiates a conversion sequence: 1. 2. 3. 4. 5. 6. 7. 8. The T/H stage holds the voltage at pin AIN, and the A/D conversion begins. Pin DOUT changes from high-impedance to logic-low. SCLK must be kept low during the conversion. The internal SAR stores the data during the conversion process. Pin DOUT going high indicates the conversion process has completed. The rising edge of pin DOUT can be used as a framing signal. SCLK shifts the data out of this register any time after the conversion is complete. DOUT transitions on the falling edge of pin SCLK. The next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits. Since there are 10 data bits and one leading high-bit or 10 data bits, two sub bits, and one leading high-bit, at least 11 or 13 falling clock edges are needed to shift out these bits, respectively.
www.austriamicrosystems.com
Revision 1.03
12 - 21
AS1526/AS1527 Data Sheet - D e t a i l e d
Description
9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN, produce trailing zeros at DOUT and have no effect on the conversion process. 10. For minimum cycle time, clock out the data with 10.5 clock cycles at full speed using the rising edge of DOUT as the EOC signal. Pull CSN high after reading the conversion's LSB. After the specified minimum time (tCS) CSN can be pulled low to initiate the next conversion.
Figure 25. Serial Interface Standard Cycle Timing Diagram
CSN SCLK
DOUT Interface Conversion In Progress Hold tCONV 7.5s Cycle Time 0s EOC
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
Idle
Clock Out Serial Data Sub Bits Track 12.5 x 0.476s = 5.95s Total = 13.7s
Trailing 0s
Idle
Track/Hold Track Stage
Hold 0s tCS 0.24s
Figure 26. Serial Interface Minimum Cycle Timing Diagram
CSN
SCLK
DOUT Interface Track/Hold Stage Cycle Time Idle Track Conversion In Progress Hold tCONV 7.5s 0s EOC
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Clock Out Serial Data Track 10.5 x 0.476s = 5s Total = 12.74s
Idle Hold tCS 0.24s
Figure 27. Detailed Serial Interface Timing Diagram
CSN tCSO SCLK tDV DOUT tSTR Internal Track/Hold Track/Acquire tAP Hold Track/Acquire tCONV B0 tCS
tCH tDO tCL S1 S0
tTR
www.austriamicrosystems.com
Revision 1.03
13 - 21
AS1526/AS1527 Data Sheet - D e t a i l e d
Description
Transfer Function
The data output from the AS1526/AS1527 is binary (unipolar), and Figure 28 depicts the nominal transfer function. Code transitions occur midway between successive integer LSB values.
Note: If VREF = +2.50V, then 1 LSB = 2.44mV (2.50V/1024). Figure 28. Unipolar Transfer Function
11...111 11...1110 11....101 Full Scale = VREF Zero Scale = 0 1LSB = VREF/1024 Full Scale (FS) Transition
00...011 00...010 00...001 00...000 0 1 2 3 Input Voltage AIN FS - 3/2LSB
Reducing Supply Current
Power consumption can be reduced significantly by powering down the devices between conversions. Figure 30 shows a plot of an average supply current versus sampling rate. Wake-up time (tWAKE) can also factor into reduced power consumption. tWAKE is defined as the time from when pin SHDNN is deasserted to the time when a conversion may be initiated (see Figure 29).
Figure 29. Shutdown Sequence Timing Diagram
Complete Conversion Sequence CSN tWAKE
SHDNN
DOUT Conversion 0 Power-Up Shutdown Conversion 1 Power-Up
For the AS1526 using the internal reference, tWAKE depends on the time in shutdown mode (see Figure 31) since the external 4.7F reference bypass capacitor slowly loses charge during shutdown. The wakeup time for AS1526 and AS1527 using an internal reference are largely dependent on the external reference's power-up time. The wakeup time for the ADC itself from shutdown mode is approximately 4s.
www.austriamicrosystems.com
Output Code
Revision 1.03
14 - 21
AS1526/AS1527 Data Sheet - D e t a i l e d
Description
Figure 30. Supply Current vs. Sampling Rate
10000
Figure 31. Powerup Time vs. Time in Shutdown
800 700
Internal Reference
Supply Current (A) .
1000
Internal Reference
. Power-Up delay (s)
600 500 400 300 200 100 0 0.001
External Reference 3V 3V
100
10
1
0.1 0.1 10 1000 100000
0.01
0.1
1
10
Sam pling Rate (s ps )
Tim e in Shutdown (s )
Internal 2.5V Reference (AS1526)
The AS1526 internal 2.5V reference output is connected to pin REF and also drives the internal DAC (see Figure 24 on page 11). REF output can be used as a reference voltage source for other components and can source up to 400A. The internal reference is enabled by pulling pin SHDNN high. Letting SHDNN float disables the internal reference, which allows the use of an external reference (see External Reference on page 15). Pin REF should be bypassed with a 4.7F capacitor as shown in Figure 23 on page 11. Larger capacitors increase wake-up time when the devices exit shutdown mode (see Layout Considerations on page 18)
External Reference
Both devices can operate with an external reference at pin REF. The external reference should be within the +1.0V to VDD voltage range to achieve specified accuracy. The minimum input impedance is 18k for DC currents.
Note: To use an external reference with the AS1526, disable the internal reference by letting pin SHDNN float.
During conversion, the external reference should be capable of delivering up to 250A of DC load current and have an output impedance 10. The recommended minimum value for the bypass capacitor is 0.1F. If the reference has higher output impedance or is noisy, bypass it close to pin REF with a 4.7F capacitor.
www.austriamicrosystems.com
Revision 1.03
15 - 21
AS1526/AS1527 Data Sheet - A p p l i c a t i o n
Information
9 Application Information
Initialization
When power is first applied, and if SHDNN is not pulled low, it takes the fully discharged 4.7F reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. With an external reference, the initialization time is 10s after the power supplies have stabilized.
Note: A/D conversions must not be started during initialization of the AS1526/AS1527.
Serial Interface
The AS1526/AS1527 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0). Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time.
Serial Interface Configuration
The AS1526/AS1527 serial interface can be configured with the following procedure: Put the microprocessor's serial interface into master mode (so that it generates the serial clock). Select a clock frequency up to 2.1MHz. Keeping SCLK low, pull CSN low via one of the microprocessor's general-purpose I/O lines. Monitor DOUT for its rising edge to determine the EOC, or wait the maximum conversion time specified before activating SCLK. 5. Activate SCLK for a minimum of 11 clock cycles. The first falling clock edge produces the MSB of the conversion. Output data transitions on the falling edge of SCLK, and is available in MSB-first format at pin DOUT. Observe the SCLK to DOUT valid timing characteristic. Data can be clocked into the microprocessor on the rising edge of SCLK. 6. CSN should be pulled high at or after the 13th falling clock edge. If CSN remains low, trailing zeros are clocked out after the LSB. 7. With CSN = high, wait the minimum specified time, tCS, before initiating a new conversion by pulling CSN low. If a conversion is aborted by pulling CSN high before the conversion's end, wait for the minimum acquisition time, tACQ, before starting a new conversion. Note: CSN must be held low until all data bits are clocked out. 8. Data can be output in two bytes or continuously (see Figure 34 on page 17). The bytes contain the result of the conversion padded with one leading 1, two sub-bits, and trailing 0s. 1. 2. 3. 4.
SPI and Microwire Interfaces
When interfacing the AS1526/AS1527 to a microprocessor's SPI or Microwire interface (see Figure 32 and Figure 33), set SPI control registers CPOL = 0 and CPHA = 0.
Figure 32. SPI Serial Interface Connections
8 SCK SCLK 7 I/O CSN 6 MISO DOUT
SSM
CPU
AS1526/ AS1527
www.austriamicrosystems.com
Revision 1.03
16 - 21
AS1526/AS1527 Data Sheet - A p p l i c a t i o n
Information
Figure 33. Microwire Serial Interface Connections
8 SK SCLK 7 I/O CSN 6 SI DOUT
CPU
AS1526/ AS1527
A conversion process begins on the falling edge of CSN (see Figure 34). DOUT goes low, indicating a conversion is in progress. Wait until DOUT goes high or until the maximum specified conversion time elapses before starting another conversion. Two consecutive 1-byte reads are required to retrieve the full 10+2 bits from the devices. Output data transitions occurs on the falling edge of SCLK, and is clocked into the microprocessor on the rising edge of SCLK. The first byte contains a leading 1, and seven bits of conversion result data. The second byte contains the remaining three bits of conversion result data, two sub-bits, and three trailing zeros.
Figure 34. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)
1st Byte Read SCLK CSN tCONV DOUT EOC D9 MSB D8 D7 D6 D5 D4 D3 D2 D1
2nd Byte Read
D0 LSB
S1
S0
High-Z when CSN is High
QSPI
When interfacing the AS1526/AS1527 to a microprocessor's QSPI interface (see Figure 35), set QSPI control register CPOL = CPHA = 0.
Figure 35. QSPI Serial Interface Connections
8 SCK SCLK 7 CSM CSN 6 MISO DOUT
SSM
CPU
AS1526/ AS1527
www.austriamicrosystems.com
Revision 1.03
17 - 21
AS1526/AS1527 Data Sheet - A p p l i c a t i o n
Information
Unlike the SPI interface, which requires two 1-byte reads to acquire the 10 data bits from the AS1526/AS1527, QSPI allows the minimum number of clock cycles necessary to clock in the data. The devices require 11 clock cycles from the microprocessor to clock out the 10 data bits with no trailing zeros or 13 clock cycles from the microprocessor to clock out the 10 data bits and two sub-bits with no trailing zeros (see Figure 36).
Note: The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz. Figure 36. QSPI Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CSN tCONV EOC High-Z when CSN is High
DOUT
D9 MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
S1
S0
Layout Considerations
The AS1526/AS1527 require proper layout and design procedures for optimum performance.
! !
Use printed circuit boards; wirewrap boards should not be used. Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other (especially clock traces). Digital traces should not run beneath the AS1526/AS1527. Use a single-point analog ground at GND, separate from the digital ground (see Figure 37). Connect all other analog grounds and DGND to this star ground point for further noise reduction. No other digital system ground should be connected to this single-point analog ground. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the AS1526/AS1527 high-speed comparator. Bypass this supply to the single-point analog ground with 0.1F and 4.7F bypass capacitors (see Figure 37). The bypass capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise.
! !
!
Figure 37. Recommended Ground Design
+3V
+3V
Digital Circuitry
Power Supplies
GND
DGND 5
GND 4.7F 10 (Optional) +3V 0.1F +
GND
AS1526/ AS1527
1 VDD
www.austriamicrosystems.com
Revision 1.03
18 - 21
AS1526/AS1527 Data Sheet - A p p l i c a t i o n
Information
Package Drawings and Markings
Figure 38. 8-pin SOIC-150 Package
Notes:
Symbol
A1 B C D E e H h L A ZD A2
Min
0.10 0.36 0.19 4.80 3.81 1.27BSC 5.80 0.25 .041 1.52 0 0.53REF 1.37
Max
0.25 0.46 0.25 4.98 3.99 6.20 0.50 1.27 1.72 8 1.57
1. Lead coplanarity should be 0 to 0.10mm (.004") max. 2. Package surface finishing: (2.1) Top: matte (charmilles #18-30). (2.2) All sides: matte (charmilles #18-30). (2.3) Bottom: smooth or matte (charmilles #18-30). 3. All dimensions exclusive of mold flash, and end flash from the package body shall not exceed 0.24mm (0.10") per side (D). 4. Details of pin #1 identifier are optional but must be located within the zone indicated.
www.austriamicrosystems.com
Revision 1.03
19 - 21
AS1526/AS1527 Data Sheet - O r d e r i n g
Information
10 Ordering Information
The devices are available as the standard products shown in Table 5.
Table 5. Ordering Information Type Description Delivery Form Package
AS1526-BSOU AS1526-BSOT AS1527-BSOU AS1527-BSOT
Single-Supply, Low-Power, 73ksps A/D Converter with Internal +2.5V Reference Single-Supply, Low-Power, 73ksps A/D Converter with Internal +2.5V Reference Single-Supply, Low-Power, 73ksps A/D Converter Single-Supply, Low-Power, 73ksps A/D Converter
Tubes Tape and Reel Tubes Tape and Reel
8-pin SOIC-150 8-pin SOIC-150 8-pin SOIC-150 8-pin SOIC-150
www.austriamicrosystems.com
Revision 1.03
20 - 21
AS1526/AS1527 Data Sheet
Copyrights
Copyright (c) 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact
www.austriamicrosystems.com
Revision 1.03
21 - 21

▲Up To Search▲

Price & Availability of AS15261

	To Download AS15261 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .